1. Field of Invention
This invention relates generally to semiconductor wafer manufacturing, and, more particularly, to photolithography and methods for producing the optimal critical dimension and overlay process window on a single chip.
2. Background of the Invention
Photolithography has a broad range of industrial applications, including the manufacture of semiconductors, flat panel displays, micromachines and disk heads. In many of these applications, multiple patterns are formed over, or on top of, one another. For example, integrated circuits may be made by using a series of photolithographic steps to form several layers of patterns on an underlying semiconductor substrate on which the integrated circuit is being made. Each layer may include patterns that are formed on or above patterns of one or more lower layers. The manufacture of semiconductor wafers requires a number of process steps to create a packaged semiconductor device from raw semiconductor material.
Photolithography requires precise alignment between the pattern on the reticle or photomask and the existing features on the wafer surface. This quality measure is known as overlay accuracy. Alignment is critical because the pattern features must be precisely transferred to the wafer from layer to layer. Overlay misalignment contributes to the total placement tolerances between the different features on the wafer surface. The range of alignment between the critical features and the range of critical dimensions for those critical features that produce functioning devices is known as overly tolerance. Overlay tolerance is determined by the points at which misalignment results in a failing device, where the features of a multilevel device either overlap other critical features at another level (if they are intended to not interact) or where they do not interact (when they are intended to interact). The tolerance between these failure mechanisms is important in understanding and controlling the photolithography process in preventing electrical shorts, opens, or other failures. Determining the overlay tolerance is beneficial to both single layer and multilayer device processing.
Various techniques are known to determine the optimum sizes of the patterns that are formed on the substrate. Process window experiments in photolithography typically consist of focus exposure matrices or wafer striping, where image size is varied across the wafer to determine the optimum image size that produces the best yielding chips. Process window experiments have no direct bearing on yield because they are used to determine the limitation of the process for each level and do not take into account the interaction between the multiple levels of a single wafer. Additionally, neither of these procedures consider the effect of varying the feature alignment within the pattern of reticle for determining the overlay tolerance for the optimum process window.
U.S. Patent Application No. 20030113641 to Leidy, et al. discloses a method for determining overlay tolerance by varying the overlay tolerance across the wafer in a manner similar to wafer striping for a constant critical dimension per each wafer. Leidy, et al. disclose exposing wafers at different critical dimensions; varying overlay tolerance for each wafer through process tooling and then using functional yield data to determine the overlay tolerance for each of the image sizes. The overlay tolerance is varied by increasing or decreasing the tooling magnification. Leidy, et al. requires processing an entire lot of wafers, where each wafer has a different critical dimension, in order to optimize the photolithography process window.
The above disclosed methods of process window optimization result in a large number of wafers routinely scraped during the optimization process. The increased consumption of raw materials during process optimization is further amplified by increasing wafer size. What is needed is a method for optimizing photolithography processing steps using a single test wafer.